1. Field of the Invention
This invention relates generally to performing powergrid analysis, and more particularly to choosing port locations for hierarchical powergrid analysis.
2. Description of the Related Art
Performing electromigration (EM) risk and voltage (IR) drop analyses of a full-chip powergrid are important steps in designing modern processors and other semiconductor devices. Many of these semiconductor devices, however, have so many circuit elements that including every circuit element in a full powergrid analysis can be impractical. To address this issue, circuit designers sometimes employ hierarchical powergrid analysis.
In hierarchical powergrid analysis, a semiconductor device's powergrid is divided into a global grid and a number of local grids, with each local grid providing power and/or signal routing internally to respective circuit portions of the semiconductor device. Both the global and local grids are generally designed to be constructed from metal layers during the semiconductor fabrication process. The metal layers forming the local grids (usually the lower metal layers) are used to interconnect groups of circuit elements in a particular area, and to provide internal power and signal routing within the group of circuit elements. The metal layers forming the global grids (usually the higher metal layers) connect the local grids and are used to provide inter-group signal and power connections.
Since a large part of the complexity involved in hierarchical powergrid analysis lies in the circuit portions served by local powergrids, the local powergrids are analyzed first. Each local analysis is generally performed by fixing one or more sites on the highest metal layer of a respective local powergrid to use as ports for connecting the local powergrid to the lowest metal layer of the global powergrid. Since powergrids are traditionally designed without ports to connect local and global powergrids, ports are defined based on local cell placement coordinates and orientation of the local cells, which implies that the highest metal of the local powergrid and the lowest metal of the powergrid will be touching at those points.
Each of the circuit portions is characterized at respective ports to obtain reduced complexity models of the circuit portions, e.g. cells served by the local powergrid. These models also usually take into account the local powergrid itself. The reduced-complexity model of each local cell is then incorporated into the global powergrid at the ports, and a global powergrid analysis is performed.
A drawback of some conventional hierarchical analysis techniques is that if a designer performs a global powergrid analysis during earlier stages of the design cycle, the exact location of the ports between the local and global powergrids may not have been fixed yet. Choosing the port locations for hierarchical powergrid analysis effectively fixes the ports at the chosen locations. Consequently, an inopportune selection of port locations can have adverse consequences on the overall circuit design, and any changes to the global powergrid design that might affect the location of the ports become problematic.